The present invention relates to the field of semiconductor manufacturing, and more particularly, to the formation of n-channel and p-channel transistors with reduced gate overlap capacitance.
Fabrication of a semiconductor device and an integrated circuit thereof begins with a semiconductor substrate and employs film formation, ion implantation, photolithographic, etching and deposition techniques to form various structural features in or on a semiconductor substrate to attain individual circuit components which are then interconnected to ultimately form an integrated semiconductor device. Escalating requirements for high densification and performance associated with ultra large-scale integration (ULSI) semiconductor devices requires smaller design features, increased transistor and circuit speed, high reliability and increased manufacturing throughput for competitiveness. As the devices and features shrink, and as the drive for higher performing devices escalate, new problems are discovered that require new methods of fabrication or new arrangements or both.
There is a demand for large-scale and ultra large-scale integration devices employing high performance metal-oxide-semiconductor (MOS) devices. MOS devices typically comprise a pair of ion implanted source/drain regions in a semiconductor substrate and a channel region separating the source/drain regions. Above the channel region is typically a thin gate oxide and a conductive gate comprising conductive polysilicon or another conductive material. In a typical integrated circuit, there are a plurality of MOS device of different conductivity types, such as n-type and p-type, and complementary MOS (CMOS) devices both employing both p-channel and n-channel devices that are formed on a common substrate. CMOS technology offers advantages of significantly reduced power density and dissipation as well as reliability, circuit performance and cost advantages.
As the demand has increased for semiconductor chips that offer more functions per chip and shorter times for performing those functions, semiconductor device dimensions have been pushed deeper and deeper into the sub-micron regime. Smaller devices readily translate into more available area for packing more functional circuitry onto a single chip. Smaller devices are also inherently advantageous in terms of shorter switching times.
There are certain factors, such as parasitic device capacitance, that impact device switching times. One relevant component of parasitic device capacitance is the gate to drain overlap capacitance which is also referred to as xe2x80x9cMiller Capacitancexe2x80x9d. The gate to drain overlap capacitance can have a significant impact on device switching speed. It is important to obtain sufficient gate overlap of source/drains for maintaining low channel resistance, but still minimize the gate to drain overlap capacitance. One of the methods that has been employed involves the use of offset spacers on the gate electrodes during source/drain extension implantation steps. The offset spacers act as a mask to prevent implantation of the dopants into the substrate directly beneath the spacers and thus, increases the separation between the source/drain extensions and the gate electrode.
The diffusivity in silicon of boron, a p-type dopant, is significantly greater than the diffusivity of arsenic, an n-type dopant. This creates a concern in semiconductor devices that contain both n-channel and p-channel transistors. The formation of an offset spacer that minimize the overlap capacitance will be optimized for only one type of transistor (e.g., n-channel) and not the other type of transistor (e.g., p-channel). In other words, providing an offset spacer with the optimum width to optimize the gate to drain overlap capacitance for an n-channel transistor will not provide the optimum spacing for a p-channel transistor optimization, due to the faster diffusion of boron in silicon.
There is a need for a method of producing n-channel and p-channel transistors on the same chip in a manner that allows optimization of the gate to drain overlap capacitance for each of the different types of transistors on the chip.
These and other needs are met by embodiments of the present invention which provide a method of forming n-channel and p-channel transistors on the same substrate, and comprises the steps of forming source/drain extensions in n-channel transistors by implanting n-type dopants a first distance away from first gate electrodes. Source/drain extensions are formed in the p-channel transistors by implanting p-type dopants a second distance away from second gate electrodes, the second distance being greater than the first distance.
By implanting the p-type dopants into the substrate a distance that is further away from the gate electrodes then the distance at which the n-type dopants are implanted, the faster diffusion of the p-type dopants is accommodated, thereby allowing optimization of the gate to drain overlap capacitance for both the n-channel transistors and the p-channel transistors. In certain embodiments of the invention, the n-type dopants are implanted in accordance with a first spacer width, and the p-type dopants are implanted in accordance with a second spacer width. In certain embodiments of the invention, the first spacer width is equal to the width of a first offset spacer on the gate electrode of the n-channel and p-channel transistors. The second spacer width is equal to the width of the first offset spacers plus the second offset spacers that are formed on the first offset spacers to form offset spacer pairs.
The other stated needs are also met by embodiments of the present invention which provide a method of forming a semiconductor device with a substrate and n-channel and p-channel transistors. This method comprises the steps of forming first offset spacers on gate electrodes on the n-channel and p-channel transistors. Source/drain extensions are implanted into the substrate at only the n-channel transistors, with the first offset spacers masking implantation into the substrate directly beneath the first offset spacers. Second offset spacers are formed on the first offset spacers. Source/drain extensions are then implanted into the substrate at only the p-channel transistors. The first and second offset spacers mask the implantation into the substrate directly beneath the first and second offset spacers.